A PCB fails, you replace it and move on. Two weeks later, the same failure hits another unit, then another. The board was not the problem — the cause behind the failure was. And replacing boards never touched it.
PCB failure analysis is a systematic investigation that identifies the root cause of a printed circuit board malfunction — not just the symptom. It answers why the board failed, not just what stopped working. That distinction is what separates a permanent fix from an expensive repeat problem.
There is a big difference between troubleshooting a single dead board and understanding a failure mechanism that could affect your entire production run. The first is a repair task. The second is an engineering problem. This article covers both — the 15 root causes most likely behind your failure, how a real failure analysis investigation works from your perspective as a client, and the exact point at which in-house diagnosis stops being enough.
What Is PCB Failure Analysis?
PCB failure analysis is the process of determining the root cause of a printed circuit board malfunction using a combination of physical inspection, electrical testing, and laboratory analysis. Its purpose is not to fix the board in front of you. Its purpose is to identify the specific mechanism that caused the failure — so you can eliminate it from your design, your materials, or your manufacturing process.
Failure Analysis vs. Repair: Not the Same Thing
Repair restores function to a specific board. Failure analysis explains why the function was lost in the first place. One addresses the outcome. The other addresses the cause; both have their place.
| Repair | Failure Analysis | |
|---|---|---|
| Question answered | Can I make this board work again? | Why did this board stop working? |
| Output | A functioning board | A root cause report + corrective actions |
| Prevents recurrence? | No | Yes — if the corrective action is implemented |
| When to use | One-off damage, obvious physical defect | Production failures, field returns, test failures |
Three Situations Where Failure Analysis Is Not Optional
Not every failed board justifies a full investigation. But in these three situations, skipping failure analysis creates a problem that compounds over time.
Production line stoppage. When boards are failing at volume and you don’t know why, every hour without a root cause costs money. Guessing at a fix and re-running production is a gamble. Root cause analysis gives you a specific corrective action — one you can implement with confidence.
Customer complaints and field returns. Products failing in customers’ hands carry reputational and liability risk. You need documented evidence of the root cause, what corrective action was taken, and how you verified the fix. A verbal explanation to a B2B client is not sufficient.
New product test failure. A prototype or first production run is failing. Before you scale, you need to know whether the problem lives in the design, the manufacturing process, or the materials. Scaling a flawed process multiplies defects — and costs.
What Are the 15 Most Common Causes of PCB Failure?
Most PCB failures are not random. They trace back to a predictable set of mechanisms — and experienced engineers have seen most of them before.
Understanding these root causes serves two purposes. It helps you design and manufacture boards that avoid these failure modes from the start. And when a failure does occur, it gives you a structured framework for narrowing down where to look first — and what to do next.
The 15 Root Causes — Overview Table
| # | Failure Cause | Origin Category | Primary Risk |
|---|---|---|---|
| 1 | Solder joint fatigue and cold joints | Assembly | Intermittent failure under thermal cycling |
| 2 | PCB delamination and blistering | Materials | Layer separation, dielectric breakdown |
| 3 | Plating voids and via barrel cracks | Manufacturing | Open circuits that pass initial testing |
| 4 | Conductive Anodic Filament (CAF) growth | Material + Environment | Progressive shorting between adjacent conductors |
| 5 | Ionic contamination | Manufacturing + Assembly | Corrosion, dendritic growth, leakage current |
| 6 | Copper trace cracking and micro-cracks | Manufacturing + Mechanical | Open circuits under stress |
| 7 | ESD and Electrical Overstress (EOS) | Handling + Operation | Latent semiconductor damage |
| 8 | Thermal stress and localized overheating | Design + Operation | Component degradation, laminate damage |
| 9 | Impedance mismatch and signal integrity errors | Design | Signal reflections, bit errors, system instability |
| 10 | Over-etching and under-etching | Manufacturing | Trace width violations, unintended shorts |
| 11 | Counterfeit or degraded components | Procurement | Parameter drift, premature failure |
| 12 | Moisture absorption and environmental corrosion | Environment | Leakage current, shorting, delamination |
| 13 | Board warpage and pad lifting | Manufacturing + Assembly | Solder joint defects, component misalignment |
| 14 | Crosstalk and EMI coupling | Design | Functional interference, intermittent failure |
| 15 | Acid traps and insufficient copper-to-edge clearance | Design | Trace necking at production, exposed copper at board edge |
Cause #1 — Solder Joint Fatigue and Cold Joints
Solder joint failure is the single most common PCB failure mechanism. It accounts for roughly 55% of all PCBA failures across industries.
The core problem is CTE mismatch. The PCB laminate, the solder alloy, and the component body each expand and contract at different rates during temperature changes. Every heat-cool cycle applies mechanical stress to the solder joint. Over hundreds of cycles, the solder deforms, fatigues, and eventually cracks. A cold joint — caused by insufficient heat during reflow — starts with poor wetting and low mechanical strength. It may pass initial testing but fails early in the field.
BGA and QFN packages are the most vulnerable. Their joints are hidden under the component body and cannot be inspected optically. A board can pass 100% functional testing and still carry solder joints that will crack within six months of field deployment.
What makes this failure deceptive: It is progressive. There is no single event that breaks the joint. It degrades gradually — resistance rises, signal integrity drops, intermittent failures begin — and by the time the failure is permanent, the board has accumulated significant field hours.
How to Fix and Prevent It:
For boards already in the field with confirmed solder fatigue, the corrective action depends on the affected package. BGA components require reballing or full component replacement — reflowing without reballing rarely restores long-term joint integrity. For QFN and LGA packages, rework under hot air with fresh solder paste is viable on a small scale, but the root cause must still be addressed.
To prevent recurrence, the fix operates at three levels:
- Design level: Add underfill to large BGA packages in high-thermal-cycling applications. Underfill mechanically bonds the component to the board, distributing stress away from the solder joints. Specify corner bonding for packages above 27mm × 27mm.
- Material level: Select solder alloys with better fatigue resistance for the target thermal range. SAC305 (Sn96.5/Ag3/Cu0.5) outperforms SAC105 in high-cycle thermal environments. For extreme temperature ranges (−55°C to 125°C), consider SAC-Bi alloys or specialty low-silver alloys with improved creep resistance.
- Process level: Validate and lock reflow profiles per paste manufacturer specifications. Cold joints result from insufficient peak temperature, too-short time above liquidus (TAL), or excessive conveyor speed. Audit solder paste volume using SPI (Solder Paste Inspection) before every reflow run. For high-reliability builds, perform accelerated thermal cycling (ATC) qualification before production release.
Cause #2 — PCB Delamination and Blistering
Delamination is the separation of PCB layers at their bond interface. Blistering is a localized version — a bubble trapped between layers that expands under heat. Both destroy the board’s structural integrity and the dielectric environment around signal traces.
The leading cause is moisture. FR-4 laminate absorbs water vapor from the atmosphere during storage or processing. When that moisture-bearing board enters a reflow oven — where temperatures exceed 250°C for lead-free processes — the trapped vapor expands rapidly. If the internal pressure exceeds the bond strength between layers, the laminate delaminates. The transition from tin-lead to lead-free soldering has made this worse: lead-free reflow peak temperatures run 20–30°C higher, reducing the margin between process temperature and laminate breakdown.
Delamination also occurs when laminates are underspecified for the application. A board running at high ambient temperatures with multiple reflow cycles needs a laminate with Tg above 170°C and Td above 340°C. Using a standard Tg 130°C FR-4 in that application is not a cost saving — it is a reliability failure waiting for a calendar date.
What makes this failure deceptive: A delaminated board often passes its initial electrical test. The layer separation may not yet bridge a conductor or create a short. The failure arrives later — after the board has been thermally stressed in service — when the separation grows to the point where it affects impedance, causes opens, or allows moisture ingress that accelerates further damage.
How to Fix and Prevent It:
A board that has already delaminated cannot be reliably repaired. Layer separation alters the dielectric properties of the stackup, and the bond cannot be restored by external heat or pressure. The correct action is to scrap the affected boards and address the root cause before re-manufacturing.
Prevention requires action at two points:
- Before assembly: Bake all bare PCBs before reflow to drive out absorbed moisture. The standard bake cycle is 125°C for a minimum of 4 hours for boards within shelf life, and 48 hours for boards that have been stored beyond the manufacturer’s recommended window or in uncontrolled humidity. Do not skip this step — it is the single most effective delamination prevention measure.
- At the design and procurement stage: Specify laminates with Tg ≥ 170°C and Td ≥ 340°C for all lead-free applications and for any board that will see more than two reflow passes. Confirm with your PCB fabricator that the laminate datasheet values, not just the material grade designation, meet your thermal requirements. Two boards both labeled “FR-4 High-Tg” can have meaningfully different Td values depending on the supplier.
Cause #3 — Plating Voids and Via Barrel Cracks
Plating voids are gaps in the copper electroplating inside plated through-holes (PTH). Via barrel cracks are circumferential fractures in the via wall. Both interrupt electrical continuity between layers. Both are nearly undetectable through standard electrical testing.
During thermal cycling, the laminate expands significantly more than the copper barrel in the Z-axis. The copper barrel is placed under tensile stress. If the plating is too thin, contains internal stress from improper chemistry, or if the via wall adhesion is poor due to inadequate desmear, that stress causes a crack. The crack starts small — a few micrometers wide. It passes ICT because the crack faces are still in contact. Over more thermal cycles, the crack widens and eventually opens into a permanent failure.
High aspect ratio vias — where the board thickness significantly exceeds the drill diameter — are particularly prone to this. The deeper the via, the harder it is to achieve uniform copper plating throughout the barrel.
What makes this failure deceptive: The board passed everything at the factory. The crack was always there — it just was not wide enough to register as a defect until field conditions stressed it open. Cross-section analysis per IPC-TM-650 is the only method that can confirm barrel integrity before the board ships.
How to Fix and Prevent It
Once a barrel crack has caused a field failure, the only repair is jumper wire rework on accessible vias, or full board replacement for internal-layer vias that cannot be accessed externally. Neither is a long-term production solution. The fix must happen at the fabrication process level.
- Specify minimum plating thickness in your fabrication notes: IPC-6012 Class 2 requires a minimum average copper thickness of 20μm in the barrel, with no individual reading below 18μm. For Class 3 applications, specify 25μm minimum average. Make this explicit in your drawing notes — do not rely on the fabricator’s default.
- Control aspect ratio during design: For standard PCB fabrication, keep the via aspect ratio (board thickness ÷ drill diameter) below 8:1. For high-reliability designs, target below 6:1. If your stackup requires higher aspect ratios, specify back-drilling or use via-in-pad with filled and capped vias, and confirm the fabricator’s capability before ordering.
- Require cross-section coupons: Include IPC-TM-650 cross-section test coupons in your panel design. These coupons are cross-sectioned and measured by the fabricator as part of first article inspection — and should be part of your qualification acceptance criteria for any new PCB supplier.
- Desmear process: Confirm the fabricator uses plasma or chemical desmear after drilling. Inadequate desmear leaves resin smear on the barrel wall that prevents copper adhesion, which is a primary cause of plating voids.
Cause #4 — Conductive Anodic Filament (CAF) Growth
Conductive Anodic Filamentation (CAF) is a slow electrochemical process that creates a conductive copper pathway inside the PCB laminate — bridging two adjacent vias, a via and a trace, or two adjacent traces — without being visible at the surface.
Four conditions must coexist for CAF to form: moisture as an electrolyte, a voltage gradient as the driving force, mobile copper ions, and a physical pathway through degraded glass-fiber-to-resin interfaces inside the laminate. The process starts when the glass-resin bond breaks down. Moisture enters the channel. Under applied voltage, copper dissolves from the anode, migrates through the aqueous pathway, and deposits as a conductive filament toward the cathode. The filament grows slowly — it can take months or years to bridge the gap fully.
By the time it causes a measurable fault, the board has been in field deployment long enough that the failure looks environmental rather than manufacturing-related. Fine pitch via patterns with spacing below 0.3mm are at highest risk.
What makes this failure deceptive: CAF passes all standard factory tests. It is invisible under optical inspection. It develops entirely after the board leaves the factory. And when it fails, it looks like a random soft short rather than a systematic manufacturing defect.
How to Fix and Prevent It:
A board with active CAF growth cannot be repaired. The filament exists inside the laminate, and there is no way to remove it without destroying the board. Affected units must be replaced. Prevention is the only viable strategy.
- Specify CAF-resistant laminates: For designs with via-to-via spacing below 0.5mm, high-voltage differentials, or deployment in humid environments, specify laminates that have passed the CAF resistance test per IPC-TM-650 2.6.25. CAF-resistant laminates use improved coupling agents at the glass-resin interface that resist degradation under moisture and voltage stress.
- Increase via spacing at the design stage: Where signal routing allows, increase via-to-via spacing to at least 0.5mm. This does not eliminate CAF risk, but it increases the path length the filament must travel before bridging — buying time and reducing failure probability.
- Control drilling parameters: CAF initiation sites are created when drill bits crack or separate the glass fiber bundles from the resin. Dull drill bits, excessive drill speeds, and too many hits per drill all increase glass-resin interface damage. Confirm the fabricator’s drill bit life policy and stack height limits.
- Apply conformal coating: For boards deployed in humid or condensing environments, conformal coating per IPC-CC-830 reduces moisture ingress at the board surface. It does not eliminate internal CAF risk, but it reduces the moisture available to activate the electrochemical process.
Cause #5 — Ionic Contamination
Ionic contamination occurs when conductive ionic residues remain on the PCB surface after manufacturing or assembly. The residues themselves may be harmless when dry. The problem begins the moment moisture is present.
Sources include: flux activators not fully removed after soldering, handling contamination from perspiration, airborne contaminants in the assembly environment, and process chemicals from PCB fabrication. Once moisture activates these residues, electrochemical migration begins — copper deposits as dendrites that grow toward adjacent conductors. Dendrites as thin as a few micrometers can bridge a 0.2mm gap and cause a short circuit. The IPC-TM-650 acceptance limit for ionic cleanliness is 10.06 μg NaCl equivalent per square inch of board surface.
Industry estimates suggest roughly 30% of PCBA field failures involve contamination as a contributing factor. Yet less than 2% of contaminated boards are returned to the fabricator for re-cleaning.
What makes this failure deceptive: The board passes all electrical tests at the factory because the environment is controlled. It enters a humid field environment. Moisture activates dormant ionic residues. The failure presents as a soft short — appearing weeks after the board enters service.
How to Fix and Prevent It:
If ionic contamination is identified as the root cause, and if the board has not yet developed dendritic shorting or corrosion damage to the copper, cleaning is a viable corrective action. Use a saponifier-based aqueous cleaning process or IPA/DI water solution appropriate for the solder flux chemistry used. After cleaning, verify cleanliness using ROSE testing or ion chromatography before re-testing the boards.
If corrosion or dendritic growth has already reached copper traces or component leads, cleaning stops the progression but does not reverse existing metallurgical damage. Those boards should be scrapped.
For prevention:
- Match cleaning process to flux chemistry: No-clean flux is not the same as no-residue flux. No-clean flux leaves residues that are acceptable under controlled conditions but can become active in humid environments. If your end-use environment involves humidity above 60% RH or temperature cycling, use a water-soluble flux with a post-assembly aqueous cleaning step.
- Implement ionic cleanliness testing as a production control: Test every production lot using ROSE testing as a minimum, and use ion chromatography when a lot fails or when the application is high-reliability. Set your internal acceptance limit below the IPC-TM-650 threshold — a common practice for Class 3 builds is to target ≤5 μg NaCl eq/in² rather than the standard 10.06 limit.
- Control handling: Require gloves during board handling after cleaning. A single bare-hand contact on a cleaned board surface can re-contaminate it above acceptable ionic limits.
Cause #6 — Copper Trace Cracking and Micro-Cracks
Micro-cracks are hairline fractures in copper traces or copper pours. Individual cracks can be less than a few micrometers wide. Standard optical inspection does not reliably detect them.
Three mechanisms create micro-cracks: manufacturing defects from over-etching or improper lamination; thermal cycling stress from CTE mismatch at layer transitions; and mechanical stress from depanelization, mishandling during assembly, or vibration in the end-use environment.
The failure mode is progressive. A micro-crack increases trace resistance slightly at first. Signal quality degrades. Resistance rises further as the crack grows. Eventually the trace opens — with increasing signal errors and functional instability before the final failure event.
What makes this failure deceptive: A trace with a 5-micron crack still measures near-zero ohms at room temperature. Under thermal expansion, the crack faces separate slightly — resistance spikes. When the board cools, they close again. This produces an intermittent failure that is notoriously difficult to capture without stress testing under controlled conditions.
How to Fix and Prevent It:
Individual micro-cracked traces can sometimes be repaired with conductive epoxy or fine-wire jumpers for low-volume rework. However, if micro-cracks are appearing systematically across a production lot, the repair approach does not scale — and the underlying process issue must be resolved first.
- Audit etching process control: Over-etching is the most common manufacturing origin of weakened traces. Verify etchant concentration, temperature, conveyor speed, and spray pressure are within the process window, and that SPC is being applied. Confirm trace width measurements at first article inspection using optical profilometry or automated AOI against the Gerber dimension.
- Add teardrops at trace-to-via junctions: Teardrops increase the copper cross-section at the point where a trace meets a via pad — the highest-stress location for thermal and mechanical crack initiation. This is a low-cost DFM addition that measurably improves resistance to trace cracking in high-cycle thermal environments.
- Review depanelization method: V-score and router depanelization both introduce mechanical stress. For boards with fine traces near the board edge or near panel breakaway tabs, specify tab routing with small breakout tabs (≤3mm width) rather than V-scoring. Consider specifying a minimum distance between breakaway tabs and the nearest copper feature.
- For vibration environments: Add support structures and conformal coating. Boards in vibration-prone applications (automotive, industrial machinery) should have component mass reviewed against PCB support span, and critical traces should be routed away from high-flex areas.
Cause #7 — ESD and Electrical Overstress (EOS) Damage
ESD is a rapid, high-voltage discharge of static electricity into the assembly. EOS is sustained electrical energy beyond a component’s maximum rating. Both damage semiconductor junctions. Both are frequently latent.
ESD produces a fast, high-voltage event — typically microseconds in duration — that creates pinhole or oxide breakdown damage. EOS produces a slower, sustained overstress — typically milliseconds or longer — that causes thermal damage: metal migration, bond wire fusing, junction melting. SEM examination of the damaged area usually distinguishes between the two based on damage morphology.
A component subjected to a damaging ESD event during assembly does not always fail immediately. It operates with degraded parameters until thermal or electrical stress in the field pushes it past the failure threshold.
What makes this failure deceptive: Standard functional testing does not detect degraded parameters. A board with latent ESD damage passes every test at the factory. The damage reveals itself only when the component encounters conditions that stress its degraded junction in the field.
How to Fix and Prevent It:
There is no way to repair ESD or EOS damage inside a semiconductor junction. Once the oxide or metallization has been damaged, the component must be replaced. For latent ESD damage specifically, even if the component appears to function, degraded breakdown voltage and increased leakage current shorten its remaining life unpredictably. Replacement is the only reliable corrective action.
Prevention operates across three areas:
- Facility controls: Operate the entire assembly area as an EPA (ESD Protected Area) compliant with IEC 61340-5-1. This means grounded workbenches and flooring, continuous wrist strap monitoring, ionizers at all operator stations, and ESD-safe packaging for all components from incoming through final test. Wrist strap testers should be verified at the start of every shift — not weekly.
- Equipment controls: Verify that all soldering iron tips measure below 2mV tip-to-ground voltage and below 5Ω tip-to-ground resistance. Improperly grounded soldering equipment is a major source of EOS damage in assembly — and it is frequently overlooked because the iron “works fine” electrically.
- Design-level ESD protection: Add TVS diodes, ESD protection arrays, or series resistors on all I/O lines that exit the board enclosure. Protection components placed close to the connector — within 300 mil — clamp transient events before they reach the sensitive IC. This does not replace facility controls but provides a second line of defense for boards deployed in harsh electrical environments.
Cause #8 — Thermal Stress and Localized Overheating
Thermal stress failure occurs when a PCB or its components operate beyond their thermal design limits — not from repeated cycling, but from sustained high temperature during operation.
High-power components — CPUs, MOSFETs, power regulators — cluster heat in one area. If the thermal design around those areas is insufficient, the local board temperature rises beyond what the laminate or components can tolerate. Component lifespans shorten dramatically — for every 10°C rise above a component’s rated maximum, its operating lifetime roughly halves under the Arrhenius model.
Insufficient thermal relief at pads also creates assembly problems: the pad cannot reach reflow temperature properly, producing cold joints that look good visually but have poor mechanical strength.
What makes this failure deceptive: Thermal failures present as gradual performance degradation — parameter drift, increased error rates, reduced output voltage — before any component actually fails. By the time an engineer uses a thermal camera to identify the hotspot, the laminate may have already been permanently altered by hundreds of hours of elevated temperature.
How to Fix and Prevent It:
For boards already in the field with confirmed thermal failures, the immediate corrective action is to replace the damaged components and assess whether the laminate has experienced permanent degradation (use DSC thermal analysis to check Tg shift). If the Tg has dropped significantly, the board must be scrapped — its structural integrity is compromised.
Long-term prevention requires thermal design corrections:
- Run thermal simulation before layout is finalized: Use simulation tools to identify hotspots before a single board is fabricated. Distribute high-power components across the board to prevent thermal density concentration. Maintain a minimum 2mm clearance between high-power components where possible.
- Design thermal vias under power pads: For ICs with exposed thermal pads (QFN, DFN, power modules), place a grid of thermal vias under the pad — minimum 0.3mm diameter, filled and capped for BGA applications — connecting the pad to internal copper planes or a bottom-side heatsink area. A well-designed thermal via array can reduce junction-to-board thermal resistance by 30–50% compared to a pad without vias.
- Select laminate Tg with margin: The laminate Tg should be at least 25°C above the maximum expected board temperature during operation. If thermal simulation shows any area of the board reaching 140°C during operation, do not use Tg 150°C laminate — use Tg 170°C or higher.
- Set correct thermal relief parameters: For reflow assembly, thermal relief spokes should be configured to balance solderability (fewer/thinner spokes = faster pad heating) against current-carrying requirement (more/thicker spokes = lower resistance). A common starting point is four spokes at 0.3mm width. Adjust based on copper weight and component thermal mass.
Cause #9 — Impedance Mismatch and Signal Integrity Errors
At signal frequencies above approximately 100 MHz, PCB traces behave as transmission lines. A trace impedance deviation of just 10 Ω from the target can cause signal reflections that degrade signal quality by 20% or more.
Impedance mismatches arise from trace width variation, dielectric thickness variation between laminate lots, via discontinuities, and incorrect termination. In DDR memory interfaces, USB 3.0, PCIe, and high-speed serial communications, these errors accumulate and produce functional failures that are extremely difficult to trace back to the PCB geometry.
What makes this failure deceptive: Impedance-related failures often pass all standard functional tests because those tests run at lower speeds or with wider margins than the actual application. The failure appears only in the end product, under real operating conditions, at the data rates the product is actually designed for.
How to Fix and Prevent It:
If impedance mismatch is the confirmed root cause in a production design, the fix depends on where the mismatch originates:
- If the PCB stackup is wrong: Work with the fabricator to adjust dielectric thickness or copper weight to hit the target impedance. This requires a stackup revision and a new fabrication run. There is no field fix for a stackup-level impedance error — rework is not possible.
- If trace widths are incorrect: A DFM correction to trace widths followed by re-fabrication resolves the issue. Run TDR (Time Domain Reflectometry) testing on the revised boards to verify impedance before assembly.
- If termination is missing or incorrect: This can sometimes be corrected at assembly level by adding or changing termination resistors. Series termination (placed near the driver) or parallel termination (placed at the receiver) — the correct type depends on the topology. Your PCB design engineer should verify the termination strategy matches the signal requirements.
For prevention, implement these at the design stage:
- Specify controlled impedance in fabrication notes with explicit tolerance (±10% is standard; ±5% for critical high-speed interfaces).
- Request TDR impedance testing on production boards as a standard acceptance criterion for controlled impedance designs.
- Keep reference plane changes (layer transitions) to a minimum for high-speed signals. Every via in a high-speed path is an impedance discontinuity. Where vias are unavoidable, use back-drilling to remove stub reflections on critical signals above 5 Gbps.
Cause #10 — Over-Etching and Under-Etching
Etching removes unwanted copper from the PCB surface to form the trace pattern. When the etching process is not controlled precisely, it removes either too much or too little copper — and both conditions create failures.
Over-etching narrows traces below their designed width, increasing resistance and reducing current-carrying capacity. Under-etching leaves excess copper — copper slivers, isolated islands, or incompletely cleared areas — that can create short circuits immediately or after vibration or thermal cycling shifts the residual copper into contact with an adjacent conductor.
Etching defects directly reflect process control quality at the fabricator. Chemical concentration gradients in the etchant bath mean boards at panel edges may etch differently than boards at the center.
What makes this failure deceptive: A 0.10mm trace that should be 0.15mm passes visual inspection and initial electrical test — but carries 44% higher resistance than designed, and fails thermally when the application pushes rated current through it.
How to Fix and Prevent It:
Over-etched or under-etched boards cannot be reworked at the trace level — copper that has been removed cannot be added back in the field. Under-etched shorts can sometimes be cleared by manual removal of the copper sliver under magnification, but this is only viable for prototype quantities. At production scale, the fabrication process must be corrected.
- Include trace width measurements in your first article inspection criteria: Specify acceptable trace width tolerance explicitly in your fabrication drawing (typically ±20% of nominal for standard designs, ±10% for controlled impedance). Require the fabricator to provide AOI or optical profilometry data confirming trace widths are within tolerance on the first production panel before full production runs.
- Request etchback and registration data for multilayer boards: For inner layers specifically, over-etching that is not caught early propagates through lamination and cannot be corrected. Inner layer AOI should be a standard step at any quality fabricator — confirm it is in their process flow.
- Design with etch compensation: Experienced PCB designers add a positive etch compensation factor to trace widths in the Gerber output — typically 0.02–0.05mm depending on copper weight and etchant process — to offset predictable etch-back. If your fabricator does not apply etch compensation automatically, discuss this in your design review.
Cause #11 — Counterfeit or Degraded Components
The component on the board is not always what the label says it is. Counterfeit components appear most frequently in legacy and end-of-life parts sourced from unauthorized distributors.
Three types are most common: remarked components (lower-grade die with higher-spec markings), cloned components (unauthorized die in a copied package), and salvaged components (pulled from scrapped electronics, re-marked with fresh date codes). Even genuine components degrade — electrolytic capacitors lose capacitance as their electrolyte evaporates, and tantalum capacitors can develop shorts under surge conditions if stored improperly.
What makes this failure deceptive: Counterfeit and degraded components often pass incoming inspection because standard visual checks and basic functional tests are not designed to detect subtle parametric degradation or internal die differences. Failure appears in the field, sometimes years after manufacture.
How to Fix and Prevent It:
When a counterfeit or degraded component is identified as the root cause, all boards from the affected lot must be evaluated. If only a specific date code or lot of components is affected, those components should be replaced across all boards from that procurement batch — not just the ones that have already failed. The failure rate will increase over time as remaining degraded components reach their stress threshold.
For prevention:
- Source exclusively through franchised distributors or authorized channels: The price premium over gray-market sources is almost always smaller than the cost of a single counterfeit-related field return. For actively manufactured parts, authorized distribution eliminates counterfeit risk almost entirely.
- Implement incoming inspection for high-risk components: For legacy or end-of-life parts where authorized sourcing is not available, perform incoming inspection including: package marking verification under magnification, lead solderability testing per J-STD-002, electrical parametric testing at temperature extremes, and — for high-value or safety-critical components — X-ray die inspection.
- Store and handle moisture-sensitive components correctly: Follow J-STD-033 for MSL (Moisture Sensitivity Level) management. Components removed from dry-pack packaging must be used within the floor life specified on the label. Bake components that have exceeded floor life before assembly. Track incoming date codes and rotate stock to prevent components from aging in inventory.
Cause #12 — Moisture Absorption and Environmental Corrosion
FR-4 laminate is not impervious to moisture. Water vapor diffuses through the substrate over time, affecting both its material properties and its electrical behavior.
Absorbed moisture lowers the dielectric constant, increases dielectric loss, provides the electrolyte for electrochemical migration (Cause #5), and contributes to delamination risk (Cause #2). Environmental corrosion from industrial chemicals, salt-laden coastal air, and acidic atmospheric pollutants attacks copper traces and solder joints — corroded copper increases trace resistance, and corroded solder joints crack earlier in the thermal fatigue cycle because the intermetallic layer has been chemically altered.
What makes this failure deceptive: A board in a climate-controlled office environment may last fifteen years without moisture-related degradation. The same design, in a coastal industrial facility, may begin showing leakage failures within twelve months. Diagnosing this requires knowing the deployment history, not just inspecting the board.
How to Fix and Prevent It:
Boards that have already absorbed moisture and show degraded insulation resistance can sometimes be recovered by baking at 60–70°C for 12–24 hours in a desiccating oven, then applying conformal coating before returning to service. This works if corrosion has not yet reached the copper. If corrosion is visible — green or black deposits on copper traces or component leads — the damage is metallurgical and cannot be reversed by drying.
For prevention, matching the protection level to the deployment environment is the key decision:
| Environment | Recommended Protection |
|---|---|
| Controlled indoor (office, data center) | No additional protection required |
| Light industrial (moderate humidity, no chemicals) | Acrylic conformal coat per IPC-CC-830 |
| Outdoor or high-humidity (>85% RH) | Silicone conformal coat or full potting |
| Marine, salt spray, or chemical exposure | Full polyurethane or epoxy potting |
- Apply conformal coating at assembly: Conformal coating is applied after final assembly and inspection. Do not apply it before cleaning if ionic contamination is present — coating over contamination traps it and accelerates corrosion under the coating.
- Specify PCB surface finish for the environment: HASL (Hot Air Solder Level) provides reasonable corrosion resistance for benign environments. ENIG (Electroless Nickel Immersion Gold) and ENEPIG provide better long-term protection for harsh environments — the gold surface passivates copper against oxidation through the product’s service life.
Cause #13 — Board Warpage and Pad Lifting
A warped board creates alignment problems during SMT assembly. Component pads that are not coplanar with the solder paste deposit produce joints that are bridged, insufficient, or completely absent on one side. Large BGAs are particularly vulnerable — a warpage of 0.3mm across a 40mm BGA package is enough to cause multiple open joints on the high side of the bow.
Warpage originates from unbalanced copper distribution between layers, residual lamination stress from incorrect curing, CTE mismatch between board and large component packages, and insufficient board thickness for the panel size being assembled.
Pad lifting occurs when copper adhesion to the substrate is locally compromised by excessive heat during rework — the pad peels away during component removal. A lifted pad is a permanent defect.
What makes this failure deceptive: Warpage defects often look fine after reflow. The component sits flat. The paste appears reflowed. But the joints on the high side of the bow are thin, stressed, and underfilled. They pass initial ICT and then fail after a small number of thermal cycles or the first mechanical shock in shipping.
How to Fix and Prevent It:
A board with confirmed warpage-induced solder joint defects must have the affected components reworked — joints that look good visually but were formed under warpage conditions have compromised integrity. Use X-ray inspection after rework on BGA components to verify joint formation.
For a lifted pad, the standard repair is a wire jumper from the via to the nearest accessible point on the trace. This is acceptable for prototype repair under IPC-7711/7721. For production, any design or process condition causing repeat pad lifting must be corrected before the next run.
Prevention:
- Balance copper distribution in the stackup: Each signal layer should have a copper pour on the corresponding opposite layer to equalize CTE forces during reflow. Use copper thieving (non-functional copper fill) in sparse areas to improve symmetry. Your PCB design tool’s copper balance analysis can identify asymmetric layers before fabrication.
- Specify bow and twist acceptance criteria: IPC-A-600 specifies maximum board bow and twist at 0.75% for SMT boards (lower is better for large BGAs). Include this in your fabrication acceptance notes. Boards exceeding this limit should be rejected before assembly, not after.
- Control rework iron temperature and dwell time: Pad lifting from rework is almost entirely preventable by setting station temperature correctly and limiting dwell time per pad to under 3 seconds for standard SMT pads. Use a wetting balance test to verify the correct temperature for each solder alloy and pad size combination.
Cause #14 — Crosstalk and EMI Coupling
Crosstalk is electromagnetic interference between adjacent signal traces. When a high-speed or high-current signal on one trace couples inductively or capacitively into an adjacent trace, it creates noise that can corrupt data, cause false triggering, or degrade analog signal accuracy.
At signal frequencies above a few hundred MHz, two closely spaced parallel traces without a reference plane between them act as a coupled transmission line pair. A 1 ns edge rate signal can inject millivolt-level noise onto an adjacent analog input or clock line — causing bit errors, unstable clock edges, or failed memory interfaces.
EMI failures — where the PCB radiates electromagnetic energy that causes regulatory compliance failure — are rooted in the same layout decisions: inadequate return path continuity, long loop areas, unshielded oscillators, and insufficient decoupling.
What makes this failure deceptive: Crosstalk and EMI failures are entirely invisible to conventional electrical testing at DC or low frequencies. A board that passes every bench test may fail EMC pre-compliance scanning at the first attempt — because the bench environment lacks the signal coupling paths present in the final product enclosure.
How to Fix and Prevent It:
If EMI or crosstalk is the root cause in a completed design, the options for correction depend on how much layout flexibility remains:
- Short-term fixes without re-layout: Add ferrite beads on affected signal lines to reduce high-frequency coupling. Add decoupling capacitors closer to aggressor ICs. Add localized shielding (copper tape grounded to the board) over radiating areas for bench-level EMC investigation.
- Layout-level corrections: Increase trace-to-trace spacing on parallel runs — the coupling between two traces decreases with the square of their separation distance. A practical rule: maintain a minimum trace separation of 3× the trace width for signal lines running in parallel for more than 10mm. Route differential pairs tightly matched and away from single-ended signals. Add a ground pour between analog and digital routing areas.
- Stackup-level corrections: Ensure every high-speed signal layer has an adjacent reference plane (ground or power). The closer the reference plane, the lower the loop inductance and the lower the EMI emission. A signal layer placed between two ground planes — a “stripline” configuration — radiates significantly less than a surface “microstrip” trace.
- Decoupling strategy: Place decoupling capacitors within 300 mil of each power pin on high-frequency ICs. Use multiple values in parallel (e.g., 100nF and 10nF) to cover a wider frequency range. Connect decoupling capacitors to the ground plane with the shortest possible via, not a long trace.
Cause #15 — Acid Traps and Insufficient Copper-to-Edge Clearance
Acid traps are a design defect — acute-angle trace junctions where etchant pools during manufacturing and continues dissolving copper after the rest of the board is done. Where two traces meet at an angle less than 90°, the sharp interior corner retains etchant and produces a localized over-etch that can narrow or sever the trace.
Insufficient copper-to-edge clearance means copper features are placed too close to the board outline. When the board is routed or scored during depanelization, the cutting process can damage the solder mask, expose bare copper, or nick the trace itself. Exposed copper at the board edge corrodes rapidly and can short to conductive enclosure hardware.
Both defects are introduced during design. Both are fully preventable with a DFM review before fabrication.
What makes this failure deceptive: Both defects produce failures that look like manufacturing quality problems. The over-etched trace from an acid trap looks like a fabricator process control failure. The corroded edge copper looks like an environmental problem. The actual cause — a design geometry error made before the board was fabricated — is invisible unless the Gerber files are examined directly.
How to Fix and Prevent It:
For acid trap failures, the affected trace cannot be repaired once the over-etch has occurred. For prototype quantities, a jumper wire can bridge the necked area. For production, the Gerber files must be corrected before re-fabrication.
For exposed edge copper, the damage depends on severity. If the solder mask is merely thin at the edge without bare copper exposure, the board may be acceptable depending on IPC class. If bare copper is exposed, apply solder mask pen or conformal coating to the edge as a temporary field measure — then correct the design for the next production run.
For prevention — both issues are caught and eliminated before fabrication with the right design rules:
- Eliminate all acute-angle trace junctions: Configure your PCB design tool’s DRC to flag any trace-to-trace or trace-to-pad junction with an interior angle below 90°. Replace acute angles with two 45° segments or a curved arc. Most CAD tools can do this automatically with a “smooth corners” or “miter” function.
- Set and enforce copper-to-edge clearance rules: A minimum clearance of 0.25mm (10 mil) from any copper feature to the board edge is a widely used standard for routed boards. For V-scored boards, increase this to 0.5mm because the V-score process applies more lateral stress than routing. Set this as a hard DRC rule in your design files — not a guideline.
- Request DFM review from your fabricator before releasing to production: Any qualified fabricator will perform a DFM check on incoming Gerber data. Ask specifically whether their DFM check includes acid trap detection and copper-to-edge clearance validation. A fabricator who cannot answer that question directly is telling you something about their process maturity.
How Is PCB Failure Analysis Actually Performed?
You have a batch of failed boards and a deadline. What actually happens next — from your perspective as an engineer or procurement manager, not from the perspective of a lab technician?
The investigation follows a fixed sequence. Non-destructive methods come first. Destructive methods follow. Each step informs the next. Skipping steps doesn’t save time — it creates gaps in the evidence chain that force you to go back and repeat work.
Step 1: Visual and Optical Inspection
Every failure investigation starts at the surface. Optical inspection under 10x to 50x magnification captures burned areas, lifted pads, corroded traces, solder bridges, cracked components, and physical damage. It is fast, it is non-destructive, and it often narrows the search zone before any other analysis begins.
But optical inspection has a hard limit. It cannot see inside the board. It cannot detect cracks smaller than a few micrometers. It cannot evaluate what is happening under a BGA package. When the failure has no visible surface signature, it means the root cause is internal — and you need the next step.
Step 2: X-Ray Inspection
X-ray imaging is where internal failures become visible without cutting the board. 2D X-ray shows solder voids, gross delamination, misaligned components, and BGA joint morphology. 3D X-ray CT scanning produces a complete volumetric model of the board’s internal structure — layer by layer, via by via. This is the tool that confirms or rules out internal plating voids, BGA void percentages beyond IPC-A-610 limits, and delamination at specific layer interfaces.
X-ray analysis is non-destructive. The board is intact after this step. All image data is captured and preserved before any destructive work begins. This sequencing matters: once you cut a board for cross-sectioning, you cannot go back and re-examine the original condition.
Step 3: Electrical and Functional Characterization
Electrical testing runs alongside or immediately after visual and X-ray analysis. The goal is to characterize the failure electrically: is this a hard open, a soft short, a leakage path, or a functional degradation that only appears under load? Continuity testing, four-wire resistance measurement, insulation resistance testing under humidity bias, and full functional test all contribute to this picture.
For intermittent failures, electrical characterization often requires stress testing — thermal cycling, vibration, or humidity biasing — to increase the failure rate to a level where it can be reliably captured and measured. This is time-consuming, but it is the only way to pin down a failure mechanism that does not show up under normal operating conditions.
Step 4: Cross-Section Analysis and Advanced Laboratory Methods
When non-destructive methods have pointed to a specific location or mechanism, destructive analysis confirms the root cause. Cross-sectioning is performed per IPC-TM-650 2.1.1: the board is mounted in epoxy, ground to the target cross-section plane, polished, and examined under optical microscopy. This reveals plating thickness, barrel integrity, inner-layer registration, resin quality, and void content — things that simply cannot be confirmed any other way.
For failures involving unknown contaminants, micro-scale cracks, or material-level defects, SEM with EDS provides sub-micron imaging and elemental composition data in a single analysis session. FT-IR identifies organic contaminants by molecular fingerprint. Ion chromatography quantifies specific ionic species — chloride, fluoride, flux activators — to determine whether contamination is within IPC-TM-650 acceptance limits.
Step 5: Root Cause Report With Corrective Actions
This is the deliverable that actually matters. The report does not end with “solder joint crack found.” It ends with: why the solder joint cracked, what specific design, material, or process condition caused it, and what specific corrective action will prevent it from recurring.
A properly structured failure analysis report follows an 8D corrective action framework and includes: failure description with context, test methods and equipment used, annotated findings with measurement data, root cause determination with supporting evidence, and a corrective action plan with a verification approach. This documentation is directly usable for supplier audits, customer responses, and internal quality reviews — not just an internal memo.
In-House vs. Professional PCB Failure Analysis: When Should You Outsource?
This is the decision most engineers delay too long. You have a lab. You have a multimeter and a microscope. How far can you get on your own — and when does in-house investigation stop being enough?
The honest answer: in-house analysis covers surface-level failures efficiently. Professional failure analysis is required when the failure is internal, latent, material-level, or when the results need to hold up to external scrutiny.
Decision Table: What Each Situation Actually Requires
| Failure Scenario | In-House Feasible? | Professional Analysis Needed? | Why |
|---|---|---|---|
| Visible burn mark or obvious physical damage | Yes | No | Optical inspection + multimeter is sufficient |
| Wrong component or placement error confirmed visually | Yes | No | BOM check + visual resolves it |
| BGA solder void suspected | No | Yes | X-ray required — cannot inspect under BGA optically |
| Via barrel crack or plating void | No | Yes | Cross-section under IPC-TM-650 is the only confirmation method |
| Intermittent failure, no visible cause | Limited | Yes | Requires stress testing + SEM characterization |
| Ionic contamination root cause | Limited (ROSE test only) | Yes | Ion chromatography needed for species identification |
| CAF growth suspected | No | Yes | SEM + EDS is the only reliable detection method |
| ESD or latent semiconductor damage | No | Yes | Curve tracer + SEM required; standard functional test misses it |
| High-voltage dielectric breakdown | No | Yes | Safety requirements and calibrated HV test equipment needed |
| Customer complaint requiring documented evidence | No | Yes | In-house results lack third-party credibility |
| Supplier liability investigation | No | Yes | Independent lab with documented procedures required |
Three Situations Where Outsourcing Is Non-Negotiable
When the failure is inside the board. Any failure mode that lives below the surface — barrel cracks, plating voids, inner-layer delamination, CAF — cannot be reliably diagnosed without cross-section analysis and SEM. This requires a metallographic polishing setup, mounting consumables, SEM access, and a technician trained in sample preparation. Improvised cross-sections produce artifacts that lead to wrong conclusions.
When the failure is latent or intermittent. Latent ESD damage, CAF growth, and early-stage solder fatigue pass functional testing and then fail in the field. Diagnosing them requires characterization tools — curve tracers, SEM, thermal cycling chambers with in-situ electrical monitoring — that most in-house labs do not have. If your board passed all your tests and still failed in the field, you are dealing with a failure mode that requires professional equipment.
When the results must be credible to someone else. If the analysis is being used to resolve a customer complaint, support a warranty claim, evaluate a supplier, or inform a product liability decision, the investigation must come from a source with documented procedures, calibrated equipment, and no conflict of interest in the outcome. Analysis done by the same team that built the board will not satisfy an external client — regardless of how rigorous it actually was.
What Should You Prepare Before Sending Your Board for Failure Analysis?
Most delays in failure analysis happen before the boards arrive. Missing information forces analysts to make assumptions — and assumptions slow down the investigation and introduce error. Getting your submission package right can cut your turnaround time in half.
Proper preparation is not a formality. The more context you provide, the faster and more accurately the root cause can be identified. Here is exactly what to prepare.
The Complete Submission Checklist
1. A Specific Failure Description
“It doesn’t work” tells the analyst nothing. A useful failure description answers these questions:
- What specifically is not functioning? (Symptom, not your assumed cause)
- Under what conditions does the failure occur? (Power-on, after thermal stress, at elevated ambient temperature, after X hours of operation)
- How consistently does it fail? (100% of boards? 5%? Intermittently at unknown rate?)
- At what point in the product lifecycle does it fail? (During production test? Early field deployment? After extended use?)
- Is there any environmental context? (High humidity, vibration, chemical exposure, temperature cycling)
2. Sample Quantity — Both Failed and Known-Good
Send a minimum of 3–5 failed boards and 2–3 known-good boards from the same manufacturing lot. Known-good reference samples are not optional. Without them, the analyst cannot distinguish between a defect and an intended manufacturing characteristic. This single omission is responsible for more inconclusive failure reports than any other.
3. Design and Manufacturing Documentation
| Document | Why It Matters |
|---|---|
| Gerber files | Allows analyst to compare as-built geometry against design intent |
| Bill of Materials (BOM) | Enables component verification and sourcing history review |
| Schematic | Provides electrical context for functional characterization |
| Assembly drawings | Confirms component orientation and placement references |
| Test records | Establishes baseline — what the board looked like before it failed |
| Reflow profile | Required to assess whether thermal processing contributed to the failure |
| Solder paste datasheet | Required to evaluate paste performance and void content expectations |
4. Manufacturing History (If Known)
Provide the PCB fabricator name, board lot number, date codes, and any known process deviations or material changes made before this production lot. If a process change — new laminate supplier, reflow profile adjustment, board cleaning chemical substitution — preceded the onset of failures, that correlation is critical information.
What Happens When Information Is Missing?
The analyst will still work with what you provide. But incomplete submissions lead to additional information requests, longer turnaround, and sometimes inconclusive results. A failure analysis is only as strong as the context surrounding it. An analyst with full documentation can often narrow the investigation to two or three likely failure modes before touching the board. An analyst with no documentation is starting from zero.
How Does IWDF Solutions Approach PCB Failure Analysis?
Most failure analysis providers give you a report and stop there. You receive a root cause determination, and then you need to find someone else — another design house, another fabricator — to actually fix the problem. That handoff introduces delays, miscommunication, and new variables.
IWDF Solutions is a PCB manufacturer. Failure analysis is the first step in a resolution process — not a standalone service. When we identify the root cause, we have the capability to fix it in the same facility, with the same team.
Our Analysis Workflow
Intake and Documentation. Every board is logged, photographed in its as-received condition, and assigned to a dedicated engineer before analysis begins. We review your failure description and identify the most likely failure hypotheses based on the symptoms provided. This pre-analysis step prevents unnecessary destructive work.
Non-Destructive Analysis. We start with optical microscopy and proceed to X-ray inspection. For BGA assemblies and boards with suspected internal defects, we use 2D and 3D X-ray CT scanning. All image data and findings are documented before any destructive steps are taken.
Electrical Characterization. We run continuity testing, isolation resistance measurement, and full functional testing in parallel with physical inspection. For intermittent failures, we apply controlled thermal cycling and humidity bias stress to reproduce the failure under monitored conditions.
Destructive Analysis. When non-destructive methods have pointed to a specific failure zone or mechanism, we proceed with cross-sectioning per IPC-TM-650, SEM/EDS for elemental analysis, FT-IR for organic contamination identification, and ion chromatography for ionic species quantification. All preparation parameters are documented.
Root Cause Report and Corrective Action. We deliver a written report following the 8D corrective action framework. The report includes failure description, test methods, annotated findings with measurement data, root cause determination with supporting evidence, and specific corrective actions with a verification plan.
What Our Deliverables Include
| Report Section | Content |
|---|---|
| Failure Description | Customer-provided context combined with analyst observations on as-received condition |
| Test Methods | Equipment used, applicable standards (IPC-TM-650, IPC-A-610, IPC-A-600) |
| Findings | Annotated images, dimensional measurements, comparison to known-good samples |
| Root Cause | The specific physical or chemical mechanism — not a category, but the actual cause |
| Corrective Actions | Design revision recommendations, process adjustments, or material substitutions |
| Verification Plan | How to confirm the corrective action has resolved the failure mode |
One Team From Failure to Fix
If the root cause is a design issue, our PCB design team revises the layout, updates the impedance stackup, or redesigns the affected circuit. If it is a manufacturing process issue, we implement the corrective action in our own production line — and verify it through a qualification build. If it requires a material substitution, we qualify the new material and confirm performance through testing before full production.
You manage one supplier relationship from failure investigation through corrective action and re-manufacture. That is what a one-stop service means in practice.
Send us your failed samples and a failure description. We will assess the case, confirm the analysis scope, and provide you with a timeline and cost estimate within 24 hours.
Conclusion
PCB failures rarely come from nowhere. Solder joint fatigue, ionic contamination, via barrel cracks, CAF growth, ESD damage — every mechanism on this list has a specific cause and a specific fix. The difference between a one-time repair and a permanent resolution is whether you identified that cause before the next batch shipped.
Circuit board failure analysis is not a cost — it is the mechanism that stops the same problem from recurring across thousands of units. The engineering investment in a proper root cause investigation is almost always smaller than the cost of a second production failure, a customer return campaign, or a product liability event.
If your board is failing and you are not yet certain why, that uncertainty is the most expensive thing on your desk right now. The faster you replace it with a confirmed root cause and a verified corrective action, the faster production stabilizes and customer confidence is restored.
IWDF Solutions provides the full path from failure to fix — failure analysis, design revision, re-fabrication, and PCB assembly — under one roof. If you have failed boards, send them to us with a failure description. We will tell you what caused the failure, what needs to change, and how we can implement that change for you.
Frequently Asked Questions
Q1: What is the difference between PCB failure analysis and PCB testing?
PCB testing checks whether a board meets its electrical and functional specifications. Failure analysis investigates why a board that failed its test — or passed its test and then failed in the field — is not working correctly. Testing gives you a pass or fail result. Failure analysis gives you a root cause and a corrective action.
Q2: How long does a PCB failure analysis take?
It depends on the failure mode. A non-destructive analysis covering optical inspection and X-ray for a clear assembly defect typically takes 1–2 business days. A full investigation involving cross-sectioning, SEM/EDS, and ion chromatography takes 5–10 business days. Cases involving intermittent failures that require stress testing to reproduce can take 2–3 weeks. We provide a timeline estimate after reviewing your samples and failure description.
Q3: How much does professional PCB failure analysis cost?
Cost depends on the scope of analysis required. Non-destructive analysis is significantly less expensive than a full destructive investigation with SEM and ion chromatography. At IWDF Solutions, we assess each case individually and provide a cost estimate before any work begins. The cost of skipping failure analysis — repeated production failures, field returns, customer complaints — is almost always higher than the investigation cost.
Q4: Can you analyze boards that you did not manufacture?
Yes. We regularly analyze boards manufactured by other suppliers. Many clients specifically request independent analysis to evaluate a third-party manufacturer’s quality. We treat all samples and design files as confidential. We can sign an NDA before reviewing any proprietary documentation.
Q5: What if the failure is intermittent and I cannot reproduce it?
Intermittent failures are the hardest to analyze — and the most important. Send us both failed boards and known-good reference boards. If the failure is not immediately reproducible, we use stress testing — thermal cycling, humidity biasing, mechanical flexing — to increase the failure rate to a level where it can be captured and characterized under controlled conditions.
Q6: Should I send the full board or just the failed section?
Send the complete board whenever possible. Cutting the board before analysis can destroy evidence — particularly for ionic contamination, ESD damage, and CAF growth, which are often located away from the visible failure point. If the board is unusually large, contact us first and we will advise on the minimum sample size needed.
Q7: What IPC standards does IWDF Solutions reference for failure analysis?
Our procedures reference IPC-TM-650 for test methods (including cross-section analysis 2.1.1 and ionic cleanliness testing), IPC-A-600 for bare PCB acceptance criteria, IPC-A-610 for assembled board acceptance across Class 1, 2, and 3 reliability tiers, and ANSI/ESDA/JEDEC JS-001 for ESD sensitivity classification. Root cause reports follow an 8D corrective action framework compatible with ISO 9001, IATF 16949, and AS9100.
Q8: If IWDF Solutions finds the root cause, can you also implement the fix?
Yes. This is the core advantage of working with an integrated manufacturer. If the root cause is a design issue, our PCB design team revises the affected files. If it is a manufacturing process issue, we implement and verify the corrective action in our own facility. If it requires a material change, we manage qualification testing before returning to full production. Failure analysis and resolution are handled by a single team — no hand-offs, no gaps.
