Designing a printed circuit board (PCB) might seem straightforward when viewed on a screen, but what looks correct in CAD software can quickly fail in the real world. From spacing errors to pad misalignments, small oversights can create large problems—causing prototype failures, halting production, or compromising final product quality. This article unpacks 15 common design traps we’ve seen in real projects and provides concrete ways to catch and correct them—before your boards hit the fab line.
The most common PCB design mistakes include incorrect trace widths, poor pad sizing, lack of design for manufacturability (DFM), and overlooked spacing rules. These issues lead to prototype failures, production delays, and board rework. Avoiding them involves using correct design rule checks (DRC), reviewing IPC guidelines, and collaborating with manufacturers early to validate stackups, materials, and tolerances.
Let’s walk through these one by one—each based on real experiences with production-level boards—to help you build more reliable designs from the start.
Wrong Trace Geometry: Why Sizing Matters More Than You Think
Trace geometry refers to the width and spacing of the copper routes that connect your components. Designers often default to a standard width—like 6 mils—without thinking about current load, signal speed, or thermal factors. In one project, a client used 5-mil traces for both signal and power lines in a dense layout. The board passed visual checks but failed under load when the traces couldn’t handle 2A of current.
How to avoid it:
- Use the IPC-2221 trace width formulas or trusted calculators to determine proper widths for your required current and copper weight.
- For external layers, a 10°C rise with 1oz copper needs ~10 mil width per amp. Double-check this if you’re handling >1A.
- For impedance-controlled signals, calculate trace width and spacing using stackup parameters. You’ll often use tools like Polar Si8000 or built-in calculators in Altium/OrCAD for single-ended and differential pair impedance.
- Avoid abrupt width changes. Use tapered transitions if changes are necessary (IPC-2152 recommends 3:1 length-to-width taper ratio).
Pads That Are Too Small (or Too Large): The Land Pattern Trap
Many designers assume that part libraries are always correct. But manufacturers change package specs and dimensions, and libraries can become outdated. In one case, a client used a standard 0603 footprint—but their parts were from a supplier with a slightly different pitch. This caused tombstoning during reflow.
Too-small pads reduce solderability and increase the risk of open circuits. Too-large pads can lead to misalignment or tombstoning, especially for small passives.
How to avoid it:
- Create land patterns using IPC-7351B standards. Use naming conventions (e.g., C for chip, R for resistor, P for passive) and calculate toe/heel/side fillet dimensions.
- If using Altium, use the IPC-compliant footprint wizard to auto-generate SMT packages with built-in tolerances.
- Always download 3D step files from vendors and verify actual dimensions vs footprint on a dummy board. Use overlays and 3D clearance tools in CAD.
- For BGAs, ensure pad size includes solder ball collapse allowances (check IPC-7095) and match stencil aperture to prevent solder starvation or bridging.
Too Tight Component Placement: When Density Becomes a Risk
While tighter layouts may seem elegant or efficient, they often create manufacturing headaches. I once reviewed a design where components were packed to maximize space on a small enclosure board. But during assembly, pick-and-place machines struggled to handle the dense component regions, and rework was nearly impossible.
Tightly packed components can lead to solder bridges, insufficient thermal relief during reflow, and higher chances of shorts during rework.
How to avoid it:
- Use pick-and-place machine specs to define minimum component clearance (usually 0.25–0.5mm for SMT parts).
- Allow at least 1.0mm around large components (like connectors or electrolytic caps) to accommodate placement heads and rework tools.
- Run component clearance checks in your CAD tool (Altium: DRC > Component Clearance rule).
- For double-sided boards, group all reflowed components on one side if possible to reduce stencil complexity and process cost.
Neglecting the 3W Rule: Unintended Crosstalk in Signal Lines
The 3W rule says spacing between signal traces should be at least 3 times the width of the trace to minimize crosstalk—interference between adjacent signals. In high-speed or analog-sensitive circuits, neglecting this rule leads to signal integrity issues.
I saw a mixed-signal audio board that worked perfectly in simulation but had noise issues on the mic input during field testing. The traces were close—about 1W—and running in parallel for long distances. Crosstalk caused unwanted high-frequency coupling.
How to avoid it:
- Maintain 3W spacing between adjacent signal traces. For a 6 mil trace, keep at least 18 mils of clearance.
- For critical nets (clocks, high-speed buses), increase spacing to 5W or more, especially over long trace runs.
- Use stripline or microstrip routing with solid reference planes to confine return current.
- For differential pairs (USB, LVDS, HDMI), use controlled impedance differential routing (e.g. 90 ohm for USB) and maintain trace length matching within 10 mils.
Poor Via Placement and Overuse of Vias
Vias are essential but easy to abuse. Too many vias add inductance and resistance—bad for high-frequency signals or power delivery. Poor via placement under pads (a common beginner mistake) can wick solder away during reflow, leaving joints dry.
One power board I reviewed had power routed through five stacked vias, creating voltage drops and heating. The client couldn’t understand why the regulator got hot until we simulated the parasitic resistance from the via chain.
How to avoid it:
- Use via-in-pad only with filled and capped vias (check with the fab house, adds cost).
- For power traces, use multiple low-impedance vias with large drill sizes (≥0.3mm) and solid thermal connections.
- Avoid routing critical high-speed signals through more than two vias if possible. Each via introduces ~0.1–0.2nH inductance.
- Use via stitching on GND planes every 50–100 mils for high-speed or RF designs to ensure return current paths.
- Ensure a minimum annular ring of 6 mil per IPC-2221 for standard vias (more if fab supports fine-line features).
Over-Reliance on Auto-Routing Tools
Auto-routing tools are great for quick layout previews—but they shouldn’t replace human judgment. I’ve reviewed boards where the autorouter created needlessly long traces, unnecessary vias, and awkward 90° turns that would cause signal reflections.
Auto-routers don’t consider thermal balance, return current paths, or EMI. They also miss out on critical design-for-manufacturing (DFM) elements.
How to avoid it:
- Set clear design constraints before using the autorouter: define trace width, clearance, layer priorities, and via cost.
- Manually route critical signals (clocks, differential pairs, memory buses) to control length, impedance, and return paths.
- Use push-and-shove routing features (Altium, KiCAD, OrCAD) to manually adjust dense zones without autorouter clutter.
- After auto-routing, run post-layout cleanup to eliminate long loops, unnecessary vias, or zigzag patterns.
Copper Pours with No Clear Planning
Filling empty board areas with copper seems smart for reducing EMI and providing ground returns. But poorly connected copper islands—especially unstitched planes—can act as antennas.
A client’s IoT device had inconsistent RF performance. We discovered an isolated copper island under the antenna, unintentionally acting as a resonator.
How to avoid it:
- Connect all copper pours directly to ground or power nets using multiple vias (stitching every 0.5–1 inch).
- Avoid unconnected copper islands (also called “floating copper”); these act like antennas at RF frequencies.
- Set minimum copper-to-copper spacing (clearance between pour edge and signal traces) to 10 mils or as per IPC-2221.
- In CAD, configure copper pour settings for thermal relief or solid fill, depending on current and thermal requirements.
Wrong Stackup for Signal Integrity and Thermal Balance
Choosing a 2-layer board when the design calls for 4 is tempting to save cost—but it often causes more problems than it solves. Poor stackup leads to impedance mismatch, uncontrolled return paths, and insufficient thermal dissipation.
One medical device prototype failed FCC tests due to uncontrolled emissions. The issue traced back to a 2-layer board routing USB lines without a continuous ground plane underneath.
How to avoid it:
- Work with your fab to define a stackup early—confirm number of layers, prepreg types, copper weights, and dielectric thicknesses.
- Use controlled impedance stackups for USB, HDMI, DDR, and RF signals. Match signal and reference layers for consistency.
- Follow ground-signal-ground layer sandwiching for stripline routing. This minimizes EMI and return path issues.
- For high-current designs, use 2 oz copper inner layers for better thermal balance, and validate with thermal simulation tools like TRM or Ansys SIwave.
Lack of Proper Design for Manufacturability (DFM)
Even if a board works, it may not be manufacturable at scale. Issues like component shadowing, non-standard footprints, and unsolderable angles lead to production delays.
I’ve seen well-designed boards rejected by CM (contract manufacturers) due to unconventional pad shapes and non-standard fiducial placements.
How to avoid it:
- Use free DFM tools from your fab to validate spacing, drill holes, mask-to-pad clearance, etc.
- Follow IPC-A-610 for solder joint acceptability and IPC-7351 for footprint standards.
- Avoid odd-shaped pads, extreme aspect ratio holes (hole depth: diameter >10:1), or tight pad-to-edge placements.
- Add fiducials, silkscreen alignment marks, and polarity indicators for automated assembly.
Solder Mask Overlaps and Openings Misaligned
A tiny mistake in your solder mask layer can ruin your whole board. If the solder mask opening overlaps a via, it can lead to solder wicking. If the mask is too narrow, it may prevent good solder joints.
One project suffered frequent open circuits because the solder mask was misaligned, partially covering SMT pads.
How to avoid it:
- Set solder mask expansion to ~2–3 mils larger than the pad in CAD settings. This ensures complete exposure.
- For via-in-pad, either tent (cover with mask), plug and cap (via-in-pad plated over), or keep a solder mask dam to avoid wicking.
- Run a Gerber preview using a viewer like GerbView or your CAM tool to check the alignment of pads vs. mask openings.
- Avoid placing silkscreen text over pads or vias—your fab may remove it automatically.
Ignoring Fab House Capabilities
Every fabrication house has minimum trace width, spacing, hole size, and annular ring requirements. Sending a board outside these limits will result in rejection or extra cost.
A startup once chose a 3 mil trace/space rule assuming it was “standard.” Their fab only supported 6 mils without HDI pricing. The board had to be re-laid, delaying their beta launch.
How to avoid it:
- Download and review your fab’s design capability chart before layout: pay attention to minimum trace/space, via sizes, solder mask dams, and copper-to-board-edge rules.
- Set your DRC rules accordingly in your CAD tool (e.g., 6/6 mil trace/space, 0.3mm via drill, etc.).
- If using HDI or microvias, confirm laser drilling, sequential lamination, and stacked via support in advance.
- Stick with standard material (FR4) and standard thickness (1.6mm) unless performance requires otherwise.
No Clearance Between Copper and Board Edges
Traces running too close to board edges can peel during depaneling or break under mechanical stress. I’ve seen power planes get exposed when a board was V-scored too aggressively.
How to avoid it:
- Maintain at least 20 mils (0.5mm) clearance between all copper features (traces, fills, pads) and the PCB outline.
- If the board has V-scoring or breakouts, increase edge clearance to 0.8–1.0mm to account for rough depaneling cuts.
- Define a keep-out zone in your CAD tool around the board outline. Most tools allow setting this globally.
Wrong or Missing Decoupling Capacitor Placement
Decoupling caps must be close to power pins—but too often, I see them far away, routed through vias, or grouped. This creates ineffective noise suppression and power instability.
How to avoid it:
- Place decoupling caps within 100 mils of the IC’s power pin, with direct trace to the pad (no vias if possible).
- For high-speed ICs or MCUs, use a 0.1uF ceramic cap (X7R) close to each VCC/GND pair. Add bulk caps (~10uF) for slower transients.
- Route power traces from the cap to the IC, not vice versa—this ensures transient current is supplied by the cap.
- Use solid ground planes under ICs to minimize inductance.
Unclear or Incomplete Documentation for Handoff
Even if your PCB design is technically flawless, poor documentation can cause miscommunication, production errors, or assembly delays. This mistake happens when teams send only Gerber files, forgetting to include fabrication notes, assembly drawings, or version control.
In one case, a CM received a set of Gerber files without a clear fabrication drawing—so they used default drill tolerances. The resulting PCBs had slightly oversized mounting holes that caused loose mechanical fits and vibration issues in the final product.
How to avoid it:
- Always include a complete fabrication drawing that outlines:
- Board size and thickness
- Stackup and layer count
- Copper weight
- Surface finish (e.g., ENIG, HASL)
- Drill sizes and tolerances
- Controlled impedance specs (if applicable)
- Provide a well-labeled BOM with part numbers, package types, and any alternates.
- Add an assembly drawing showing component orientations, polarity, test points, and any “do not populate” (DNP) parts.
- Use version control in filenames (e.g.,
Project_X_RevB_2025.06.18.zip) to avoid confusion between revisions. - Supply readme.txt or PDF build instructions if you expect special treatment or constraints.
No Prototype Review Before Final Production
Moving directly from layout to full production without physical validation introduces huge risk. Minor issues—like swapped connector pins, mismatched footprints, reversed polarity, or mechanical misfits—can remain invisible in design files but become expensive to fix once thousands of units are built.
One team went straight from CAD to 1,000 units. Post-assembly, they discovered a swapped pin on a connector—unfixable without board rework.
How to avoid it:
- Always order a pilot run of 5–10 units before mass production. Validate footprints, connector orientation, signal routing, and power-up behavior.
- Perform first article inspection (FAI) under a microscope to confirm solder joint quality and alignment.
- Test for shorts, opens, and power sequencing with a bed-of-nails tester or manual probing.
- Use design checklists (you can request mine!) to ensure design rules, BOM matching, and mechanical clearance were all verified.
Summary
Designing a PCB that performs well and is easy to manufacture takes more than electrical knowledge—it requires a production mindset. By avoiding these common pitfalls through DRC checks, footprint reviews, and manufacturer collaboration, you can ship better boards faster and avoid unnecessary setbacks.
Would you like a DFM/DRC checklist to review before you send your files to the fab? Drop us a message—IWDF Solutions are happy to help.
